1. Field of the Invention
The present invention generally relates to a method and apparatus for fabricating devices on semiconductor substrates. More specifically, the present invention relates to a method and apparatus for performing an etch process in a semiconductor substrate processing system.
2. Description of the Related Art
Ultra-large-scale integrated (ULSI) circuits may include more than one million micro-electronic devices (e.g., transistors, capacitors, and the like) that are formed on a substrate (e.g., silicon (Si) wafer) and cooperate to perform various functions within the device. Manufacture of ULSI circuits generally comprises processes where one or more material layers of a film stack on the substrate are etched (e.g., plasma etched) to form structures of the devices being fabricated.
One problem associated with a conventional etch process is the non-uniformity of a lateral etch rate across the substrate due to a substrate edge effect. Herein lateral etch rate non-uniformity is defined as a ratio of a difference between the maximal and minimal lateral etch rate to the sum of such values across the substrate. More specifically, the lateral etch rate at peripheral locations (i.e., near an edge of the substrate) is higher than the lateral etch rate near a center of the substrate. Non-uniformity in the lateral etch rate results in non-uniformity in the critical dimensions of the structures formed by the etch process.
During the etch process, non-volatile by-products passivate sidewalls of the structures being formed and, as such, reduce the etch rate. Non-uniformity of the etch rate across the substrate is caused by a higher concentration of the by-products near the center of the substrate than in the peripheral region. In operation, a concentric pattern of exhaust pumping in the etch process chamber results in a low concentration of the by-products near the edge of the substrate and, correspondingly, in a high local lateral etch rate.
Structures being formed using the conventional etch process are typically over-etched in the peripheral region that may extend about 10-20 mm from the edge of the substrate. Such a region represents approximately 19-36% and 13-25% of usable real estate for the 200 mm and 300 mm substrate, respectively. A loss of accuracy for topographic dimensions (e.g., critical dimensions (CDs), or smallest widths) of the etched structures in the peripheral regions of the substrates may significantly affect performance and increase costs of fabricating the integrated circuits and micro-electronic devices.
Therefore, there is a need in the art for an improved method for etching material layers with high uniformity of a lateral etch rate across a substrate in manufacture of micro-electronic devices.